1. Technical Field
The present invention relates to digital circuits in general, and more particularly, to digital frequency multiplier circuits.
2. Description of Related Art
Frequency multiplier circuits are commonly utilized in electronic devices, such as radio receivers/transmitters, to multiply a base frequency of an oscillator by a pre-defined number. The multiplied output frequency can then be amplified and/or sent to a final drive stage for delivery to another electronic device, such as a transmitting antenna.
Based on an input reference signal, a digital frequency multiplier circuit utilizes a voltage controlled oscillator (VCO), which is tuned to a harmonic of the input frequency signal, along with a frequency divider and a phase-locked loop (PLL) to generate a desired output frequency. The frequency divider located within the feedback loop of the PLL is coupled to the output of the VCO. The output of the frequency divider is thus fed back into a phase detector (PD), which compares the divided frequency to the reference signal and sends a signal to the VCO that increases the output frequency until the divided frequency is equal to the reference frequency. As a result, the output frequency of the frequency multiplier circuit is stabilized at a value equal to the reference frequency multiplied by the value of the frequency divider.
Conventional digital frequency multiplier circuits employ complicated algorithms and/or hardware to acquire, align, and lock an output frequency at a desired value. Such frequency multiplier circuits can consume large amounts of power and occupy precious physical space on circuit boards. Consequently, it would be desirable to provide an improved digital frequency multiplier circuit.